The present disclosure relates to a semiconductor integrated circuit device including a core region and an I/O region.
In recent years, semiconductor integrated circuits have further increased in scale to have an increasing number of input and output signals. Therefore, in a device including such a semiconductor integrated circuit, namely, a semiconductor integrated circuit device, arranging external connection pads, configured to transmit and receive, for example, signals to or from the outside of the device, in a single row along the periphery of the semiconductor integrated circuit device may define the area of the semiconductor integrated circuit device, resulting in an increase in its area.
Japanese Unexamined Patent Publication No. 2007-305822 discloses a configuration for a semiconductor integrated circuit device in which pads are arranged in multiple rows. In this configuration, the pads through which power is supplied to the core region are arranged to form an innermost one of the multiple rows, and connected to power supply interconnects of a core power supply.